1. Field of the Invention
The present invention relates to a DC-DC converter, the control circuit thereof and, the control method thereof. More particularly, the present invention relates to a DC-DC converter of a synchronous rectifier type, wherein the efficiency thereof under a light load condition is improved, the control circuit thereof, and the control method thereof.
2. Related Art
FIG. 19 is a block diagram showing the configuration of a general DC-DC converter. The DC-DC converter of FIG. 19 includes a conversion block 2 and a control block 3. The conversion block 2 converts an input voltage VIN to an output voltage VOUT of a specific magnitude. In addition, the control block 3 outputs a signal VCONT controlling the output of the conversion block 2 using the output VOUT of the conversion block 2 as a feedback signal, and includes a detecting circuit 4, an error amplifier circuit 5, a reference voltage source 6, a comparison circuit 7 and an oscillation circuit 8.
The detecting circuit 4 detects the output voltage of the conversion block 2. The error amplifier circuit 5 compares a detection consequence VO of the detecting circuit 4 with a predetermined reference voltage VREF fed from the reference voltage source 6, amplifies the difference between VO and VREF and outputs the amplified voltage difference as a voltage value VE. The reference voltage source 6 supplies the reference voltage VREF to the error amplifier circuit 5. The control block 3 controls the conversion block 2 so that detected the voltage value VO of the output voltage VOUT becomes equal to the reference voltage VREF. The comparison circuit 7 compares an output voltage VE from the error amplifier circuit 5 with an output signal VOSC of the oscillation circuit 8, generates a control signal VCONT based on the result of comparison, and outputs the control signal VCONT to the conversion block 2. The oscillation circuit 8 supplies a signal VOSC (a triangular wave or a saw tooth wave) of a specific frequency to the comparison circuit 7.
FIG. 20 through 23 show general examples of the conversion block 2. FIG. 20 shows an example where a DC-DC converter 1 is a buck converter. The buck converter decreases the output voltage VOUT with respect to the input voltage VIN, and obtains the output voltage VOUT lower than the input voltage VIN.
In the circuit example of FIG. 20, an inductor 14a (L) is connected in series to the input, and a capacitor 15a (C) is connected in the next stage in parallel (to the inductor 14b (L).) In addition, a switch 12a (S1) is connected between the input and the inductor 14a (L). A synchronous rectifier switch 13a (S2) is connected to the connecting point of the main switch 12a (S1) and the inductor 14a (L), and between the connection point and the ground GND. And a drive circuit 11a is connected to drive the switches 12a (S1) and 13a (S2).
When the drive circuit 11a turns the switch 12a (S1) on and turns the switch 13a (S2) off based on the control signal VCONT from the control block 3, a current IL flowing through the inductor 14a (L) increases (namely energy is stored in the inductor 14a (L)). When the switch 12a (S1) is turned off and the switch 13a (S2) is turned on, the current IL decreases (namely energy of the inductor 14a (L) is released). The magnitude of the output voltage VOUT can be controlled by controlling the switching of the switches 12a (S1) and 13a (S2).
FIG. 21 shows an example where the DC-DC converter 1 is a boost converter. The output voltage OUT is increased with respect to the input voltage VIN in the configuration of FIG. 21, and the output voltage VOUT higher than the input voltage VIN is obtained.
In the circuit example of FIG. 21, the inductor 14b (L) is connected in series to the input, and a capacitor 15b (C) is connected in the back stage in parallel (to the inductor 14b (L)). In addition, the main switch 12b (S1) is connected between the right side of the inductor 14b (L) and the ground GND. The synchronous rectifier switch 13b (S2) is connected between the inductor 14b (L) and the capacitor 15b (C). A drive circuit 11b is connected to drive the main switch 12b (S1) and the synchronous rectifier switch 13b (S2).
FIG. 22 shows an example where the DC-DC converter 1 is a buck-boost converter. In the configuration of FIG. 22, the output voltage VOUT for the input voltage VIN is increased or decreased, and the output voltage VOUT higher or lower than the input voltage VIN is obtained.
In the circuit example of FIG. 22, an inductor 14c (L) is connected in parallel with the input and the switch 12c (S1). A capacitor 15c (C) is connected in the back stage in parallel to the input. In addition, the main switch 12c (S1) is connected between the input and the inductor 14c (L), and a synchronous rectifier switch 13c (S2) is connected between the inductor 14c (L) and the capacitor 15c (C), and a drive circuit 11c is connected to drive the main switch 12c (S1) and the synchronous rectifier switch 13c (S2).
FIG. 23 shows an example where the DC-DC converter 1 is a flyback converter. A transformer 16 is used in FIG. 23, and the output voltage VOUT is increased or decreased with respect to the input voltage VIN.
In the circuit example of FIG. 23, the transformer 16 is installed such that the input is on the primary side of the transformer 16, and a capacitor 15d (C) is installed on the secondary side of the transformer 16. And the main switch 12d (S1) is connected to the primary coil of the transformer 16. The synchronous rectifier switch 13d (S2) is connected between the secondary coil of the transformer 16 and a capacitor 15d (C). A drive circuit 11d is connected to drive the main switch 12d (S1) and the synchronous rectifier switch 13d (S2).
The operation of the DC-DC converter 1 having any of the configurations shown in FIG. 20 through 23 will be briefly described with reference to FIG. 24 below. Driving signals VC1 and VC2 for driving the switches S1 and S2 are fed from the drive circuit 11 (11a, 11b, 11c, or 11d) in any of FIG. 20 through 23, and the switches S1 and S2 are turned on and off alternately.
The main switch S1 and the synchronous rectifier switch S2 of FIG. 20 through 23 are semiconductor switching elements such as a MOSFET and a bipolar transistor, or mechanical switching elements such as a relay circuit.
In the drawings, the switch S1 (S2) is ON when the driving signal VC1 (VC2) is HIGH, and the switch S1 (S2) is OFF when the driving signal VC1 (VC2) is LOW, as described below. However, the switch S1 (S2) may be set, with no problem, to be OFF when the driving signal VC1 (VC2) is HIGH and the switch S1 (S2) to be ON when the driving signal VC1 (VC2) is LOW depending on the characteristics of the element used for the switch S1 (S2).
When the driving signals VC1 and VC2 are input as shown in FIG. 24 and the main switch S1 and the synchronous rectifier switch S2 repeat ON and OFF states alternately, the voltage VL across the inductor L (or the coil which constitutes the transformer) theoretically exhibits the waveforms as shown in FIGS. 24(a) and 24(b).
In FIGS. 24(a) and 24(b), the voltage VL across the inductor L has a square waveform synchronized with the drive voltages VC1 and VC2. The positive and negative voltages of the voltage VL are respectively represented by VL1 and VL2, respectively. When the DC-DC converter 1 is the buck converter of FIG. 20, VL1=VIN−VOUT and VL2=−VOUT, respectively. When the DC-DC converter 1 is the boost converter of FIG. 21, VL1=VIN and VL2=VIN−VOUT, respectively. And, when the DC-DC converter 1 is the buck-boost converter of FIG. 22 or the flyback converter of FIG. 23, VL1=VIN (the primary side) and VL2=VOUT (the secondary side) respectively. Here, VIN and VOUT are the input voltage and the output voltage of the DC-DC converter 1 respectively.
The inductor current IL increases monotonically when the switch S1 is turned on and the switch S2 is turned off. The inductor current IL decreases monotonically when the switch S1 is turned off and the switch S2 is turned on. An average value ILAVG of the inductor current IL is equal to IOUT for the buck converter of FIG. 20. The average value ILAVG of the inductor current IL is equal to IINAVG for the boost converter of FIG. 21. And, in the case of the buck-boost converter of FIG. 22 or the flyback converter of FIG. 23, the average value ILAVG is equal to IINAVG+IOUT. In this regard, IIN, IINAVG and IOUT are respectively the input current, the average value of the input current IIN, and the output current of DC-DC converter 1.
A converter of a synchronizing rectification type has two operating states depending on whether the inductor current IL is negative for a certain period or not. FIG. 24(a) shows operational waveforms when the inductor current IL is always positive and FIG. 24(b) shows operational waveforms when the inductor current IL is negative for a certain period.
In FIG. 24(b), the inductor current IL has a negative polarity during a period T. During the period when the inductor current IL is negative, generally the output current IOUT is small. In this case, because the ratio of losses caused by the devices constituting the DC-DC converter 1 to the output power becomes large, the efficiency is impaired.
To obviate the problems described above, during the period when the inductor current IL is negative, a method for reducing the losses of the switch and the inductor is employed. The losses of the switch and inductor caused by the negative current during the period T of FIG. 24(b) are reduced by interrupting the negative current of the inductor current IL as shown in FIG. 25.
In FIG. 25, the inductor current does not exhibit negative polarity by appropriately setting a period for which VC1 and VC2 are OFF simultaneously. FIG. 26 is a block diagram showing a general configuration of a DC-DC converter, provided with a negative current interruption circuit for interrupting the negative current of the inductor.
In the DC-DC converter of FIG. 26, a negative current detecting circuit 21 is disposed as the negative current interruption circuit. The negative current detecting circuit 21 detects IL of 0 A or lower and outputs a signal to the driver circuit to turn off the switch S2.
FIG. 27 shows an example of the negative current detecting circuit 21 in FIG. 26. The circuit shown in FIG. 27 includes a comparator 22 that compares signal IL indicating the magnitude of the inductor current IL with the reference signal IREF. The comparator sets signal VCOMP at HIGH and output the signal VCOMP set at HIGH to the driver circuit. The drive circuit turns off the switch S2 based on the signal VCOMP set at HIGH.
In FIG. 27, the signal IL is fed into the inverting input of the comparator 22 and the signal IREF is fed into the non-inverting input. Alternatively, the input scheme may be reversed with no problem. In this case, when the signal IL became equal to or less than the signal IREF, a LOW signal is fed as the signal VCOMP and the drive circuit turns the switch S2 off based on the signal VCOMP set at LOW.
In the circuit of FIG. 27, the inductor current IL and 0 A are compared by setting IREF at 0 A. When the signal IL is equal to or less than 0 A, the signal VCOMP is set at HIGH and the switch S2 is turned off.
However, the method described above causes a time delay between the time point at which the inductor current IL becomes 0 A and the time point, at which the switch S2 is turned off, due to the delays caused between the response of the negative current detecting circuit 21 or the drive circuit II and the switch S2. Therefore, the inductor current IL at the time point at which the switch S2 is really turned off is very much lower than 0 A.
FIG. 28 shows the state described above. In FIG. 28, the time delay caused between the negative current detecting circuit 21, or the drive circuit 11, and the switch S2 is represented by td. The inductor current IL falls down to −ILov, since the switch S2 is turned off after the time delay td has passed from the time when the inductor current IL becomes 0 A.
It is necessary to shorten the time delay td to reduce the negative current. For shortening the time delay, it is necessary to make the negative current detecting circuit 21 and the drive circuit 11 operate at a high speed. However, when these circuit operations are speeded up, the currents consumed in the negative current detecting circuit 21 and the drive circuit 11 increase. In particular, it may be requested to shorten the time delay td to several nanoseconds in a small DC-DC converter operating in a MHz frequency range. For realizing the time delay of several nanoseconds, the power consumptions of the negative current detecting circuit 21 and the drive circuit 11 soar from several milliwatts to several tens of milliwatts. Thus, the power consumptions of the circuits 11 and 21 become higher than the output power of the DC-DC converter in the operating state in which a period exists for which the inductor current IL has negative polarity. Therefore, the effects of interrupting the negative inductor current IL are canceled.
In addition, it is conceivable to estimate the negative magnitude of the inductor current IL during the time delay td in advance and to set IREF of FIG. 27 such that IREF>0 A, so that IL may be equal to 0 A at the time point at which the switch S2 is turned off. However, the gradient at which the inductor current IL decreases varies depending on the operating state of the DC-DC converter, such as the input voltage and the output voltage. Therefore, if IREF is set appropriately for a gentle gradient of the inductor current IL, a negative current will flow when the inductor current IL varies at a steep gradient. If IREF is set appropriately for the steep gradient of the inductor current IL, the switch S2 will be turned off before IL reaches 0 A when the inductor current IL varies at a gentle gradient, and the period from the time point at which the switch S2 is turned off to the time point at which IL reaches 0 A will increase. Therefore, the period for which a current flows to a parasitic diode of the switch S2, that is the period from the time point at which the switch turning-off of S2 is turned off to the time point, at which IL is 0 A, is elongated, and efficiency is impaired.
As described above, in the case in which the negative current detecting circuit is configured as shown in FIG. 27, the value of the inductor current IL varies when the switch S2 is turned off depending on the operating state of the DC-DC converter, and, therefore, the accuracy of negative current interruption is impaired.
Japanese Patent No. 3501491 discloses a method of improving the efficiency when a light load is placed on the output of the DC-DC converter. The configuration of Japanese Patent No. 3501491 conducts intermittent switching which stops the switching operation of a switching element for a certain period under light load. However, this method causes many ripples in the output voltage. In addition, the negative current of the inductor cannot be intercepted accurately. Further, Japanese Patent No. 3501491 discloses a method for intercepting the negative current of the inductor. However, this method employs a configuration similar to that shown in FIG. 27, and therefore the same problems as described above are caused.